Low Cost Nonrecursive Digital Filter Structures

This paper presents a novel method of hardware reduced fast FIR filter structure for parallel data processing.In general, arithmetic operation modules such as adder and multiplier modules, consume much power, energy, and circuit area. The power consumed by the adder structure is also very significant while designing a low power filter. The proposed low power multipliers and low power adders are used to reduce dynamic power consumption of digital FIR filter. Supported by a review of literature, the proposed methodology is superior and economical. The results show improved performance in terms of cost reduction, which has practical implications in terms of applications Keywords— FIR filter design, FDA Tool, Low Power VLSI